1. Field of the Invention
The invention herein relates in general to a dual bus interface printed circuit board (PCB) and more particularly to a PCB provided with both a PCI-X (Peripheral Component Interconnect-Extended) bus interface and a PCI-E (Peripheral Component Interconnect-Express) bus interface.
2. Background Art
In the field of I/O Interconnect, PCI (Peripheral Component Interconnect) is a widely adopted I/O bus standard in a wide variety of computer platforms. To meet the growing demand for bandwidth by new applications, PCI has gone through several changes in the last decade leading to extension standards such as PCI-2.2 and PCI-X (PCI-Extended). These extension standards however are all built on the same architecture, protocols, signals, and connector as the conventional PCI, the reuse having been mainly supported by the combination of backward compatibility and the ease of migration from the conventional PCI to the newer standards.
The conventional PCI architecture is based on a multi-drop, parallel bus implementation, with one local bus being shared by multiple peripheral devices to communicate with the central processing unit (CPU). When first developed, the PCI architecture solved some of the limitations of the previous bus standards such as ISA (Industry Standard Architecture) and EISA (Extended ISA), by allowing direct access of peripheral devices to the CPU. However, with the exponential growth of CPU power, bus technology based on the conventional PCI architecture is becoming more and more a bottleneck to enhanced system performance. The main reason for that being that a shared bus technology suffers from a scalability problem, limiting the number of peripherals that can be efficiently supported by a system.
At its current state, the conventional PCI bus technology is theoretically very close to its practical limits, with only minor performance gains possible at large costs in form factor. It is for this reason therefore that the conventional PCI architecture is slowly giving way to a new standard known as the PCI-E (PCI-Express) standard.
The PCI-E architecture is based on a series of point-to-point connections, with each connection employing a packet-based transfer scheme and supporting bidirectional communication. To meet the varying bandwidth needs of different system components, PCI-E can be easily scaled from one to 32 lanes, with a single lane providing 250 MB/sec of dedicated bandwidth in each direction. In addition to providing ample bandwidth, PCI-E also supports advanced power management, hot plugging, and its packet-based transfer protocol allows for time dependent data delivery and quality of service arbitration for high priority data streams.
Although PCI-E clearly provides major performance improvements compared to the conventional PCI standard and its extensions (parallel PCI), serial PCI-E is not backward compatible with parallel PCI, and the shift from parallel PCI to PCI-E is likely to be a slow one. It is expected that parallel PCI will coexist in many platforms with PCI-E to support today's lower bandwidth applications, until a compelling need, such as a new form factor, causes a full migration to fully PCI-E systems.
Foreseeing the coexistence of PCI and PCI-E in future platforms, chip makers have been designing dual PCI-X/PCI-E chipsets that can be operated with either of the two bus standards.
Currently available PCBs, however, are designed for use with only a single bus standard, providing a single bus connector per card. As a result, dual bus chipsets have to be mounted on multiple PCB variations to support the various bus interface types, denying the user the interface duality of the chipset component, and running higher fabrication costs to chipset manufacturers.
The likely coexistence of the PCI-X and the PCI-E bus standards in future computer platforms necessitates efficient solutions to ensure the interoperability of the two. As PCI-E is not backward compatible with the conventional PCI standard, of which PCI-X is an extension, chipset manufacturers currently resort to carrying multiple PCB variations of the same product in order to support various bus interfaces. This solution is clearly a costly and inefficient one from a fabrication process point of view.
What is needed therefore is a dual interface PCB card that provides both PCI-X and PCI-E functionality.